A 5.83 Pj/Bit/Iteration High-Paraliel Performance-Aware Ldpc Decoder Ip Core Design for Wimax in 65 Nm Cmos

By: Material type: ArticleArticleDescription: 2623-2632 pSubject(s): In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Item type Current library Call number Vol info Status Date due Barcode
Articles Articles Periodical Section Vol.E96-A, No.12 (Dec. 2013) Available

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