A 5.83 Pj/Bit/Iteration High-Paraliel Performance-Aware Ldpc Decoder Ip Core Design for Wimax in 65 Nm Cmos
Zhao, Xiongxin Chen, Zhixiang Peng, Xiao Zhou, Dajiang
A 5.83 Pj/Bit/Iteration High-Paraliel Performance-Aware Ldpc Decoder Ip Core Design for Wimax in 65 Nm Cmos - 2623-2632 p.
Wimax
Bit-Serial
Fuliy Paraliel
A 5.83 Pj/Bit/Iteration High-Paraliel Performance-Aware Ldpc Decoder Ip Core Design for Wimax in 65 Nm Cmos - 2623-2632 p.
Wimax
Bit-Serial
Fuliy Paraliel