Normal view MARC view ISBD view

Glitch Power Minimization By Selective Gate Freezing

Benini, L

Glitch Power Minimization By Selective Gate Freezing - 287-298 p.

Subjects--Topical Terms:
Cmos Digital Integrated Circuits,

Print
Request article
Suggest for purchase
Send to device
Save record
BIBTEX Dublin Core ISBD MARCXML RIS
More searches

Search for this title in:
Other Databases (Google Scholar) Open Library (openlibrary.org) Pakistan Union Catalogue (pastic.gov.pk) Other Libraries (WorldCat)

Report a problem