0.13-/Um 32-Mb/64-Mb Embedded Dram Core with High Efficient Redundancy and Enhanced Testability
Kikukawa, Hirohito tomishima, Shigeki Tsuji, Takaharu
0.13-/Um 32-Mb/64-Mb Embedded Dram Core with High Efficient Redundancy and Enhanced Testability - 932-940 p.
Embedded Controlers
Redundancy in Earthquake-Resistant
Soc Infrastructure
0.13-/Um 32-Mb/64-Mb Embedded Dram Core with High Efficient Redundancy and Enhanced Testability - 932-940 p.
Embedded Controlers
Redundancy in Earthquake-Resistant
Soc Infrastructure