Normal view MARC view ISBD view

A 6-Ghz 16-Kb Li Cache in A 100-Mn Dual-Vt Technologyusing A Bitline Leakage Reduction (Blr) Technique

Ye, Y

A 6-Ghz 16-Kb Li Cache in A 100-Mn Dual-Vt Technologyusing A Bitline Leakage Reduction (Blr) Technique - 839-842 p.

Subjects--Topical Terms:
Bitline
Cell Array Architecture

Print
Request article
Suggest for purchase
Send to device
Save record
BIBTEX Dublin Core ISBD MARCXML RIS
More searches

Search for this title in:
Other Databases (Google Scholar) Open Library (openlibrary.org) Pakistan Union Catalogue (pastic.gov.pk) Other Libraries (WorldCat)