000 00455nab a2200133Ia 4500
008 230808s2003 |||||||f |||| 00| 0 eng d
100 _aYe, Y
_9794796
245 2 _aA 6-Ghz 16-Kb Li Cache in A 100-Mn Dual-Vt Technologyusing A Bitline Leakage Reduction (Blr) Technique
300 _a839-842 p.
650 _aBitline
_9769487
650 _aCell Array Architecture
_9817903
773 _d2003
_tIeee Journal of Solid-State Circuits
_x00189200
942 _cART
_o51
_pABUL KALAM Library
999 _c769697
_d769697