000			00483nab a2200133Ia 4500
008			230808s2002 |||||||f |||| 00| 0 eng d
100			_aLin, L-F _9810092
245		2	_aA 0.8-V 128-Kb Four-Way Set-Associarive Two-Level Cmos Cache Memory Using Two -Stage Wordline/Bitline-Oriented Tag-Campare (Wlotc/Blotc) Scheme
300			_a1307-1317 p.
650			_aLow Power
650			_aLow Voltage _9679283
773			_d2002 _tIeee Journal of Solid-State Circuits _x00189200
942			_cART _o51 _pABUL KALAM Library
999			_c765062 _d765062