000			00531nab a2200157Ia 4500
008			230808s2003 |||||||f |||| 00| 0 eng d
100			_aWatanabe, Takamoto _9805904
100			_aYamauchi, Shigenori _9805905
245		3	_aAn All-Digital Pll for Frequency Multiplication By 4 to 1022 with Seven-Cycle Lock Time
300			_a198-204 p.
650			_aCmos _988695
650			_aPhase-Locked Loop (Pll) _9798117
650			_aSynthesizer _9761622
773			_d2003 _tIeee Journal of Solid-State Circuits _x00189200
942			_cART _o51 _pABUL KALAM Library
999			_c759517 _d759517