000			00547nab a2200157Ia 4500
008			230808s2001 |||||||f |||| 00| 0 eng d
100			_aOsada, Kenichi _9757963
100			_aShin, Jinuk Luke _9769062
245		0	_aUniversal-Vdd 0.65-2.0-V 32-Kb Cache Using a Voltage-Adapted Timing-Generation Scheme and lithographicaliy Symmetrical Celi
300			_a1738-1744 p.
650			_aCache Memory _9143358
650			_aLow Power
650			_aSelf-Timing _9769064
773			_d2001 _tIEEE Journal of Solid-State Circuits _x00189200
942			_cART _o51 _pABUL KALAM Library
999			_c740558 _d740558