| 000 | 00520nab a2200157Ia 4500 | ||
|---|---|---|---|
| 008 | 230808s2000 |||||||f |||| 00| 0 eng d | ||
| 100 |
_aMiyano, Shinji _9768703 |
||
| 100 |
_aNamekawa, Toshimasa _9768704 |
||
| 245 | 0 | _aDynamicaliy Shift-Switched Dataline Redundancy Suitable for Dram Macro with Wide Data Bus | |
| 300 | _a705-712 p. | ||
| 650 |
_aRedundancy _9725322 |
||
| 650 |
_aDram _9757956 |
||
| 650 |
_aWide Data Bus _9768706 |
||
| 773 |
_d2000 _tIEEE Journal of Solid-State Circuits _x00189200 |
||
| 942 |
_cART _o51 _pABUL KALAM Library |
||
| 999 |
_c740428 _d740428 |
||