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		An All-Digital Phase-Locked Loop for High-Speed Clock Generation by Chung, Ching-Che Lee, Chen-Yi Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Hdl Presynthesis Optimizations Using A Tabular Model. by Li, J Gupta, R. K Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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