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		A Semi Digital Delay Locked Loop Using An Analog Based Finite State Machine by Friedman, Daniel Rhee, Woogeun Parker, Benjamin Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator by Ishii, Kiyoshi Enoki, Takatomo Shibata, Tsugumichi Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		An All-Digital Pll for Frequency Multiplication By 4 to 1022 with Seven-Cycle Lock Time by Watanabe, Takamoto Yamauchi, Shigenori Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Behavioral Modeling Approach toDesign of A Low Jitter Clock Source by Kwak, Sung-Ung Manganaro, Gabriele Cho, Seonghwan Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Phase Noise Cancellation Design Tradeoffs in Delta Sigma Fractional N Plls by Pamarti, Sudhakar Galton, I Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Design of Cmos Adaptive Bandwidth Pll/Dlls A General Approach by Horowitz, Mark A Wei, Gu-Yeon Kim, Jaeha Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Methodology for on Chip Adaptive Jitter Minimization in Phase Locked Loops by Mansuri, Mozhgan Yang, Chih-Kong Ken Hadiashar, Ali Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Fully Integrated Zero-If Transceiver for Gsm-Gprs Quad-Band Application by Duvivier, Eric Puccio, Gianni Cipriani, Stefano Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A False Lock Free Clock/Data Recovery Pll for Nrz Data Using Adaptive Phase Frequency Detector by Kunieda, H Idei, Gijun Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Dds Based Pll for 2.4 Ghz Frequency Synthesis by Lacaita, A. L Bonfanti, A Samori, C Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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