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		A 10-Gb/S Receiver with Series Equalizer and on-Chip Isi Monitor in 0.11-Um Cmos by Tomita, Yasumoto Kibune, Masaya Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Fuliy Integrated Sige Receiver Ic for 10-Gb/S Data Rate by Greshishchev, Yuriy M Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Sige Clock and Data Recovery Ic with linear-Type Pli for 10-Gh/S Sonet Application by Greshishchev, Yuriy M Source: IEEE Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Practical Measurement of Timing Jitter Contributed By A Clock and Data Recovery Circuit by Pease, Christopher Babic, Dubravko Source: Ieee Transactions on Circuits and Systems, I: Fundamental Theory and Applications Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Pll Design Technique By A Loop-Trajectory Analysis Taking Decision-Circuit Phase Margin Into Account for Over-10-Gb/S Clock and Data Recovery Circuits by Kishine, Keiji Ichino, Haruhiko Kusanagi, Satomi Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Quad 0.6-3.2 Gb/S/Channel Interference-Free Cmos Transceiver for Backplane Serial Link by Moon, Yongsam Park, Young-Soo Shin, Hyun J Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 10-Gb/S Data-Pattern Independent Clock and Data Recovery Circuit with A Two-Mode Phase Comparator by Ishii, Kiyoshi Enoki, Takatomo Shibata, Tsugumichi Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Jitter Transfer Analysis of Tracked Oversampling Techniques for Multigigabit Clock and Data Recovery by Choi, Youngdon Kim, Wonchan Jeong, Deog-Kyoon Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A Fully Integrated 43.2-Gb/S Clock and Data Recovery and 1:4 Demux Ic in Lnp Hbt Technology by Nielsen, S Case, M G Thiagarajah, R Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A False Lock Free Clock/Data Recovery Pll for Nrz Data Using Adaptive Phase Frequency Detector by Kunieda, H Idei, Gijun Source: Ieee Transactions on Circuits and Systems-Ii: Express Briefs ( for merly: Analog & Digital Signal Processing) Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 0.18-Um Sige Bicmos Receiver and Transmitter Chipset for Sonet Oc-768 Transmission Systems by Meghelli, Mounir Rylyakov, Alexander V Friedman, Daniel Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		A 40-43-Gb/S Clock and Data Recovery Ic with Integrated Sfi-5 1:16 Demultiplexer in Sige Technology by ong, Adrian Benyamin, Saied Cancio, Jason Source: Ieee Journal of Solid-State Circuits Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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