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		Optimal Wire-Sizing Function UnderElmore Delay Model with Bounded Wire Sizes by Lee, Y. M Source: Ieee Transactions on Circuits and Systems, I: Fundamental Theory and Applications Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article
		Interleaving Buffer Insertion and Transistor Sizing Into A Single Optimization. by Jiang, Y Sapantnekar, S.S Source: Ieee Transactions on Very Large Scale Intergration (Vlsi) Systems Material type: Article; Format: print Availability: Items available for loan: Engr Abul Kalam Library (1). Request article

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