Kikukawa, Hirohito tomishima, Shigeki Tsuji, Takaharu <br/><br/>
0.13-/Um 32-Mb/64-Mb Embedded Dram Core with High Efficient Redundancy and Enhanced Testability 

 - 932-940 p. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Embedded Controlers<br/>Redundancy in Earthquake-Resistant<br/>Soc Infrastructure