Ye, Y <br/><br/>
A 6-Ghz 16-Kb Li Cache in A 100-Mn Dual-Vt Technologyusing A Bitline Leakage Reduction (Blr) Technique 

 - 839-842 p. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Bitline<br/>Cell Array Architecture