Watanabe, Takamoto Yamauchi, Shigenori <br/><br/>
An All-Digital Pll  for  Frequency Multiplication By 4 to 1022 with Seven-Cycle Lock Time 

 - 198-204 p. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Cmos<br/>Phase-Locked Loop (Pll)<br/>Synthesizer