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A 0.8-V 128-Kb Four-Way Set-Associarive Two-Level Cmos Cache Memory Using Two -Stage Wordline/Bitline-Oriented Tag-Campare (Wlotc/Blotc) Scheme

Lin, L-F

A 0.8-V 128-Kb Four-Way Set-Associarive Two-Level Cmos Cache Memory Using Two -Stage Wordline/Bitline-Oriented Tag-Campare (Wlotc/Blotc) Scheme - 1307-1317 p.

Subjects--Topical Terms:
Low Power
Low Voltage

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