Esd Protection Design for Mixed Voltage I/O Buffer with Substrate Triggered Circuit
Ker, Ming-Dou Hsu, Hsin-Chyh
Esd Protection Design for Mixed Voltage I/O Buffer with Substrate Triggered Circuit - 44-53 p.
Electrostatic Discharge (Esd)
Stacked Nmos
Esd Protection Design for Mixed Voltage I/O Buffer with Substrate Triggered Circuit - 44-53 p.
Electrostatic Discharge (Esd)
Stacked Nmos